The present invention relates to a circuit arrangement for modifying pyramidal texture coordinates for three-dimensional (3-D) graphics applications and also to a display apparatus including or being driven by such a circuit arrangement, particularly but not exclusively a stereoscopic or multiple view display apparatus.
An example of such a circuit arrangement and its use in a single view (non-stereoscopic) display apparatus is described in our European patent application EP-A-0 438 195 which provides a circuit arrangement for converting pyramidal texture coordinates into corresponding physical texture memory addresses in an electronic display apparatus. The circuit arrangement comprises a pyramidal coordinate input for receiving a two-dimensional (2-D) coordinate pair and an associated level coordinate, together with means for generating from the received coordinate pair and level coordinate a corresponding physical texture memory address. The texture memory holds a pyramidal or part pyramidal array of texture element (xe2x80x9ctexelxe2x80x9d) values representing a 2-D modulation pattern (the texture) to be mapped onto surface primitives, with each level of the pyramid holding a 2-D version of the pattern filtered to a different level of resolution. Suitable filtering methods for the generation and storage of pyramidal texture arrays are described in a paper entitled xe2x80x9cPyramidal Parametricsxe2x80x9d by Lance Williams, Computer Graphics, Volume 17, No 3 (July 1983) at pages 1 to 11.
EP-A-0 438 195 is concerned with an arrangement for translating texture map addressing to allow for efficient storage of part-pyramidal arrays in a linearly addressed (one-dimensional) texture memory, with a simple offset mechanism enabling rapid indexing between corresponding areas of maps of differing resolutions.
Most 3-D graphics systems can produce auxiliary information for each pixel in the rendered image, in addition to the color and intensity, such as the depth of the nearest surface impacting each pixel as is commonly available from a z-buffer. Given depth information for the nearest surface impacting each pixel, it is possible to blur the rendered image by filtering such that the amount of blurring increases as a function of the difference between the depth associated with the pixel and some programmable depth value corresponding to a point of interest. The effect mimics what happens in the cinema when a camera focuses on a point of interest and other parts of the scene are blurred. Previously, however, systems such as that of EP-A-0 438 195 have required the blurring effect to be applied as a further processing step to the rendered and texture mapped image.
It is therefore an object of the present invention to provide a relatively simple mechanism which enables focus/de-focus effects to be incorporated during rendering and texture mapping of an image.
In accordance with a first aspect of the present invention there is provided a circuit arrangement for modifying pyramidal texture coordinates for three-dimensional (3-D) graphics applications, the arrangement comprising: a pyramidal coordinate input for receiving a two-dimensional (2-D) texture coordinate pair and an associated level coordinate; and means operable to generate a physical texture memory address based on the received 2-D texture coordinate pair and associated level coordinate, said means being arranged to generate an offset to said associated level coordinate, and to generate said physical texture-memory address from the received coordinate pair and the sum of the associated level coordinate and generated offset thereto: characterised in that said circuit arrangement further comprises an input for receiving a focal depth value, and said means operable to generate a physical texture memory address is arranged to generate said offset having a magnitude determined by the received focal depth value.
This arrangement can be applied in apparatus for the generation of images to be displayed on a conventional display such as a monitor or projection system, but is of particular interest for stereoscopic displays such as autostereoscopic screens or Virtual Reality binocular headsets as the stereo effect is reinforced by the depth cueing provided by de-focusing the texture.
In the circuit arrangement, the offset is suitably generated per pixel of an image and the focal depth value consequently specifies a relative depth difference between a depth value for the image and a depth value for each pixel. A limiter stage may be provided coupled with the texture memory address generator, the limiter acting to maintain the said sum of the associated level coordinate and generated offset thereto within a predetermined range of values.
In accordance with a further aspect of the present invention, there is provided a display apparatus comprising a host processor with associated main memory for the storage of object primitive data and texture definitions and a first display processor with associated display memory and texture memory, the host processor comprising: means for storing in the texture memory at least one pyramidal or part-pyramidal array of texel values comprising a plurality of 2-D arrays of texel values representing a given 2-D modulation pattern at at least two levels of resolution defined by respective values of a level coordinate; and means for supplying object primitive data to the first display processor, including an indication that a pattern of modulation is to be applied to the object primitive in accordance with texel values stored in the pyramidal array in the texture memory; the first display processor comprising: means for generating from the object primitive data a series of pixel addresses for application to the display memory and a corresponding series of 2-D texture coordinate pairs each with an associated level coordinate, to effect a mapping of the stored modulation pattern onto the object primitive at a level or levels of resolution defined by the associated level coordinate; and means operable to generate an offset to each said associated level coordinate, and to generate said texture memory addresses from the received coordinate pair and the sum of the associated level coordinate and generated offset thereto; characterised in that the display processor further comprises an input for receiving a focal depth value, and said means operable to generate said offsets is arranged to generate said offsets having a respective magnitude determined by the received focal depth value.
The display apparatus may further comprise a second display processor with associated display memory, the second display processor being coupled to receive the object primitive data from the host processor and comprising means for applying at least one of a horizontal and a vertical offset to the received object primitive data, means for generating from the offset primitive data a series of pixel addresses for application to the display memory. By the application of the offset, the second image of a stereoscopic pair may be provided. Where provided, the second display processor may have an associated texture memory corresponding to that of the above-mentioned first display processor, together with a respective input for receiving the focal depth value and means operable to generate said offsets. Depending on the application of the display apparatus, user operable input means may be provided coupled to the host processor, with the processor arranged to generate and vary the focal depth value in dependence on signals from the input means and output the focal depth value to the or each display processor.
In accordance with a still further aspect of the present invention, there is provided a multi-view display apparatus comprising a number of display apparatuses as described above, the display memories of which supply images to respective views of a multi-view lenticular array screen. The central views of the horizontally displaced series of viewpoints provided by the lenticular array are driven by the above-described first display processors, and the outer views being driven by the respective ones of the second display processors. In other words, the central images are each generated by a respective rendering stage whilst those towards the edge are of lower quality, being generated by post-processing techniques.